1. Field of the Invention
This invention relates to read-only memories, programmable read-only memories, and erasable programmable read-only memories, and in particular to read-only memories fabricated from insulated gate field-effect transistors in which information is stored by the phenomena of hot electron trapping.
2. Prior Art
A random access memory (hereinafter RAM) is an array of latches, each with a unique address, having an addressing structure which is common for both reading and writing. Data stored in most types of RAM's is volatile because it is stored only as long as power is supplied to the RAM. A read-only memory (hereinafter ROM) is a circuit in which information is stored in a fixed, nonvolatile manner; that is, the stored information remains even when power is not supplied to the circuit. By convention, a ROM is a circuit in which information is stored by alterations made during fabrication or processing of the semiconductor wafer, while a programmable read-only memory (hereinafter PROM) is one in which the information is stored after the device is fabricated and packaged. Erasable programmable read-only memories (hereinafter EPROM's) are PROM's which can be completely erased and reprogrammed. EPROM's typically have been fabricated from arrays of MOS transistors.
Electrically programmable ROM's fabricated using insulated gate field-effect transistors (hereinafter IGFET) have typically been of two different types. One type of electrically programmable ROM is the metal nitride oxide semiconductor structure (hereinafter MNOS). Such structures rely on charge tunneling phenomena and have been described in numerous publications. See, for example, "IEEE Transactions on Electron Devices", May 1977, Volume ED24, Number 5. (A special issue on nonvolatile semiconductor memories.)
A typical MNOS structure is shown in FIG. 1. Such a structure utilizes a very thin layer of insulating material, typically silicon dioxide, to separate a silicon nitride region and a gate electrode from the channel of the device. MNOS devices are programmed by applying a positive potential to the gate electrode while holding the source, drain, and substrate regions at a lower potential. This causes electrons in the substrate and channel regions to "tunnnel" vertically through the oxide layer and lodge in the nitride layer.
For the electrons to tunnel through the oxide, the oxide layer must be very thin, typically on the order of 20 to 30 angstroms. In addition, the electric field in the gate insulating region must be very high for efficient tunneling. The high electric field requires the use of high voltages and a relatively thin nitride layer, typically on the order of 500 angstroms.
Accurate control of the thickness of the thin silicon dioxide layer has proven difficult in a production environment, as has control of the silicon nitride film properties. Also, the high electric field required for tunneling can easily cause permanent damage to the memory cells or to peripheral circuitry, thereby reducing the yield of such devices and increasing their costs. In addition, movement of charge within the nitride and tunneling of the electrons trapped in the nitride layer back through the thin oxide can change or destroy the information stored in the device, ruining its effectiveness.
MNOS structures typically use expitaxial substrates and isolation diffusions to isolate each memory cell or groups of memory cells, depending upon the desired array organization, from surrounding cells or other peripheral circuitry. Because the tunneling effect is uniform across the full width of the gate electrode, the electrons trapped in the nitride will be almost uniformly distributed across the width of the silicon nitride layer. This results in electrically symmetrical device operation because device operation is not affected by source and drain terminal interchanges.
Another type of memory element used in forming electrically programmable ROM's is the field alterable MOS transistor structure, also known as a floating gate structure (hereinafter FAMOS type). Such structures are well known. See, for example, U.S. Pat. No. 3,500,142 entitled FIELD EFFECT SEMICONDUCTOR APPARATUS WITH MEMORY INVOLVING ENTRAPMENT OF CHARGE CARRIERS issued to D. Kahng, and D. Frohman-Bentchkowsky, Applied Physics Letter, vol. 18, page 332, 1971. An example of a FAMOS type structure is shown in FIG. 2. FAMOS type structures utilize a charge injection phenomenon in which a control gate and drain electrodes are biased to cause electrons flowing between the source and drain to pass from the substrate and collect on the floating gate electrode. The electron's momentum from the source to the drain causes most of them to be injected onto the portion of the floating gate electrode nearest the drain. Because the floating gate electrode is conductive, the electrons spread out on the floating gate as they repel each other, thereby preserving electrical symmetry with respect to the source and drain terminals.
Unfortunately, the FAMOS structure suffers from several disadvantages. A relatively thin layer of oxide or insulating material must be formed between the floating gate electrode and the control electrode. This requires carefully controlled manufacturing processes resulting in lower yields and higher costs. Additionally, programming the FAMOS structure requires relatively high voltages, for example, on the order of 25 to 30 volts. Such high voltages can cause excessive parasitic conduction and/or rupture of the thin films formed elsewhere on the wafer. Further, the high voltages required increase the complexity of the structure of the device because the source and drain must be formed with carefully controlled concentration profiles to ensure pn junction breakdown at the desired high voltages.
It has been discovered, and observed to be a limitation in IGFET design, that under appropriate biasing conditions electrons flowing between the source and drain of an IGFET can acquire sufficient energy to be injected into the insulating material between the gate electrode and the channel. Some of the injected electrons are trapped in the insulating material near the drain, causing a change in the current-voltage characteristics of the IGFET, and creating an electrically asymmetrical structure sensitive to source/drain terminal interchanges. This effect is discussed in an article entitled "N-Channel IGFET Design Limitations Due to Hot Electron Trapping", by S. A. Abbas and R. C. Dockerty, and published in the IEDM Proceedings, Washington, D.C., 1975. Abbas and Dockerty explain that the electrons flowing between the source and drain of an IGFET may under certain conditions undergo randomizing scattering motions which cause them to PG,6 move toward the interface between the silicon substrate and overlying silicon dioxide layer. Some fraction of the electrons arriving at this interface have sufficient energy to be injected into the insulating material and trapped to cause a change in the operating characteristics of the particular transistor. Abbas and Dockerty observe that the change in operating characteristics is most evident when the transistor is operated in a reverse mode, that is, with the source and drain interchanged.